Advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Accordingly, semiconductor manufacturing process advancements are driving the corresponding geometric dimensions of semiconductor devices to decreasingly smaller values. 10 micrometer (μm) gate lengths, for example, were common in the 1970's, but continuously advancing semiconductor manufacturing processes have reduced gate lengths to well below 100 nanometers (nm).
Conventional scaling of transistor geometries, however, will soon become insufficient to continue device performance advancements through the creation of smaller transistors. Thus, alternatives to device scaling are being developed, where in one alternative, the formation of ultra-thin gate structures are used to control capacitance. Other alternatives to device scaling include stress engineering, whereby carrier mobility increases within the channel of a field effect transistor (FET) are realized through the introduction of mechanical stresses that are imposed upon the channel.
In particular, a compressive stress imposed upon the channel of a p-type FET (PFET) has been shown to increase the mobility of holes within the channel of the PFET. Similarly, a tensile stress imposed upon the channel of an n-type FET (NFET) has been shown to increase the mobility of electrons within the channel of the NFET.
A conventional technique to introduce compressive, or tensile, stress within the channel of a FET is to provide structures on either side of the channel that either compress, or stretch, the channel after formation. In particular, recesses are etched into a layer of silicon on either side of a previously formed gate stack. Source and drain films are then formed within each recess, where the films may be comprised of a silicon-germanium (SiGe) alloy for PFET devices, or a silicon-carbide (SiC) alloy for NFET devices.
Since the films are epitaxially formed within the recesses, each film exhibits the same crystal lattice structure as the crystal lattice structure of the underlying silicon. However, due to the inclusion of the SiGe alloy in the PFET devices, each atom in the alloy lattice exhibits a larger separation distance as compared to the separation distance of each atom of the underlying silicon lattice. As such, a compressive stress is exerted on the channel region of the PFET between each source and drain recess, which has been shown to increase the mobility of holes within the PFET channel during the conductive state of the PFET.
Alternately, inclusion of the SiC alloy in the NFET devices causes each atom in the alloy lattice to exhibit a smaller separation distance as compared to the separation distance of each atom of the underlying silicon lattice. As such, a tensile stress is exerted on the channel region of the NFET between each source and drain recess, which has been shown to increase the mobility of electrons within the NFET channel during the conductive state of the NFET.
Conventional semiconductor processing techniques, however, tend to create adverse effects during the formation of the source and drain recesses. In particular, isotropic etchants are typically used to form the source and drain recesses where the SiGe and SiC films are formed. However, since the etchants are isotropic, the shape and undercut of the trench is controlled only by the amount of time that the source and drain regions are exposed to the etchant. Additionally, gate oxide damage and encroachment of the etchant into the silicon beneath the channel region may cause undercut during the etching process, which adversely affects the performance of the device.
Efforts continue, therefore, to identify semiconductor etching processes that provide selective etching so as to better control the shape and depth of trenches formed within the semiconductor material.